Custom Design of CXL Controller on Intel FPGA R-Tile

To meet the high bandwidth and low latency communication requirements between modern computer processors and accelerators or memories, for applications such as in data center processing, and "multi-GPU and CPU" in machine learning (ML), in the latter case though NVLink (2014) and the latest UALink (2024) are available, while CXL (Compute Express Link) has been developed in 2019 and continuously provides a cache consistent interconnect technology between CPU and device, as well as between devices. This article reports the custom design of CXL controller on Intel FPGA R-Tile architecture. The R-Tile supports PHY Interface for PCI Express (PIPE) direct mode, it can provide up to 16 SerDes (serializer / deserializer) channels. The PIPE SerDes mode interface is connected to the custom controller implemented in soft IP through the Embedded Multi-die Interconnect Bridge (EMIB). The CXL custom controller designed includes the Logic Physical Layer (PHY) and Medium Access Control (MAC), Data Link Layer (DLL) and Transaction Layer (TL), that includes the Transmitter (TX) and Receiver (RX). The custom controller design of this CXL device is expected to promote efficient data transmission, expand memory bandwidth and capacity, efficiently meet complex computing requirements, and significantly improve system performance, further verification and application are to be applied.