Simulation Optimization and Fabrication Verification Study of Ion Implantation In 12-Inch CMOS Process

This study utilizes TCAD to model and simulate the CMOS fabrication process, focusing on the impact of ion implantation parameters on critical electrical characteristics such as threshold voltage, saturation current, and breakdown voltage. Specifically, it explores the effects of dose, energy, and tilt during the Pocket Implant process. A comparative analysis of simulation result was conducted to obtain the optimal ion implantation recipe. The optimized recipe was then applied to actual fabrication, showing a high accuracy in predicting key electrical metrics. This approach provides valuable insights for optimizing 12-inch CMOS technology while reducing development time and costs.