Z²-FET Memory with Both Flash and DRAM Modes

In this study, we develop a novel memory device based on Z<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>-FET. Our memory device exhibits dual-mode operation as either flash or DRAM (dynamic random access memory) under different bias conditions. The functionality is validated through TCAD simulations. The flash memory mode is achieved by integrating an engineered gate dielectric for charge storage in the Z<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>-FET. In flash mode, data readout is innovatively achieved by applying voltage from the source in order to avoid triggering the transient feedback used in DRAM mode. In DRAM mode, the charge stored in gate capacitor is read out through feedback mechanism. The flash and DRAM modes demonstrate non-volatile and fast access speed characteristics, respectively. Eventually, a process based on fully depleted silicon-on-insulator (FD-SOI) substrate is developed to fabricate the dual-mode Z<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>-FET memory which is further subjected to preliminary measurements.