SLCF: Security-Level-Aware Microarchitectural Cleaning for Efficient Time Protection

The primary challenge in current microarchitectural security is that timing attacks can leak sensitive information across security domain boundaries, severely threatening system security. These attacks typically exploit microarchitectural features of shared processor resources (such as caches, branch predictors, etc.) to infer secret data in another security domain by measuring operation latency. While existing temporal partitioning techniques provide some protection, they generally adopt coarse-grained “one-size-fits-all” cleaning strategies that indiscriminately clear all microarchitectural states, causing significant performance degradation in high-performance out-of-order processors. This paper proposes a Security-LevelAware Cleaning Fence mechanism (SLCF) that dynamically selects the cleaning scope based on the processor’s security level: in user mode, only the L1 data cache is cleaned, while in supervisor mode, comprehensive microarchitectural state cleaning is performed. Experimental results on the OpenC910 RISC-V processor demonstrate that this mechanism effectively defends against microarchitectural timing channel attacks while controlling performance overhead to an extremely low level. The user mode SLCF successfully closes the L1D cache timing channel with an average performance overhead of only $0.53 \%$, while the supervisor mode SLCF provides comprehensive protection by closing all microarchitectural timing channels with a performance overhead of $1.18 \%$. This mechanism ensures system security while minimizing the impact of defensive measures on system performance.