Automated Layout Design for High Frequency Integrated Circuits Based on Reinforcement Learning

In this work we propose a reinforcement learning (RL) based automated layout design procedure for high frequency integrated circuits, and demonstrate its feasibility on low noise amplifier (LNA) architectures at process node 40nm Si CMOS. Given a pre-optimized design and its corresponding device blocks, a proper layout solution can be generated within 1 hour. The post-simulation result of the generated layout has a loss of no more than 5% in performance (Gain, Noise Figure, etc.) compared to pre-simulation results. The algorithm is based on Reinforcement Learning (RL) Proximal Policy Optimization (PPO) and implemented by Actor-Critic framework. The placement is done by optimizing positions and directions of each device block, routing is accomplished using A-star algorithm. The automation procedure is highly modularized and portable between different design environments and different process nodes, exhibiting great potential in solving complex high frequency placement & routing (P&R) problems.