Study on Improving Local Mismatch of 0.305μm² Small Size SRAM

Static random access memory (SRAM) is widely used in sensing applications and in a wide variety of other ASIC and system chips. In order to obtain the maximum SRAM capacity while further reducing the chip area, SRAM usually uses the minimum size allowed by the corresponding technology node. However, when the chip size is reduced, the local mismatch between adjacent transistors of the SRAM unit is also more serious, resulting in low yield of the chip. In this paper, based on the SRAM structure with mature technology and mass production, the size is miniaturized by 20% to develop a smaller size of SRAM. Based on the process and device perspective, by optimizing the core NLDD implant and hard mask for polysilicon gate etch, the local mismatch between adjacent transistors of SRAM cells are reduced, The V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">MIN</inf> (it is twenty percent lower than normal voltage) yield of SRAM test wafers are increased 130%. At the same time, the program is based on the HV mature process platform development, no additional mask, cost saving, stable and controllable, suitable for mass production.