Design of Ferroelectric FET-based Symmetric Computing-in-Memory Array with Simultaneous Weight Gradient Calculation and Weight Update for on-Chip Learning

In this work, a novel ferroelectric FET (FeFET) based symmetric computing-in-memory (CIM) array enabling simultaneous weight gradient (ΔW<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</inf>) calculation and weight update is proposed for on-chip learning with reduced latency. By utilizing stochastic computing (SC) scheme with novel bipolar pulse streams for ΔW<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</inf> calculation and utilizing the output pulses of SC for update of FeFET weights, the ΔW<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</inf> calculation and weight update of backpropagation (BP) learning are in-situ realized simultaneously for the whole array of CIM cell with special designed tri-state XNOR gate. Moreover, through the design of symmetric differential input and readout based on reference FeFET, four-quadrant vector-matrix multiplication (VMM) of configurable forward and backward propagation are implemented in the FeFET-based CIM array. Based on the design, image recognition’s neural network is demonstrated with a high accuracy of 95.33% and reduced hardware cost, showing great potential for on-chip learning.