A DFT Test Power Consumption Optimization Technology

With the rapid development of the modern integrated circuit process and the increasing scale and integration of chips, the test power consumption becomes a key challenge in the chip design and manufacturing process.If the test power consumption is too high, a series of problems may occur, such as increasing the load on the test equipment, affecting the reliability and stability of the chip, and reducing the yield of the chip.The introduction of clock gating has proved to be an effective technology for effectively reducing dynamic power consumption. This paper proposes a DFT test power consumption optimization scheme based on code combination logic to control ICGs, which provides an innovative circuit design idea for DFT to effectively implement low-power tests.