An Integrated Solution for Optimizing the I_dsat Performance of 55 nm BCD Devices

The 55 nm BCD(Bipolar-CMOS-DMOS) technology has become a critical platform for advanced mixed-signal and power ICs (integrated circuits), making the improvement of its electrical performance essential for further development. This article proposes an optimization involves adjusting the amount and sequence of gate oxide wet etching to address the issue of gate oxide over-etching and replacing the single-layer oxide structure with an ONO (Oxide-Nitride-Oxide)-based SAB (Salicide Block) structure to mitigate spacer damage caused by intensive wet processes. Both measures significantly contribute to reducing I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dsat</inf> and their combined application demonstrates a stronger synergistic effect. This integrated approach offers a practical and effective solution for optimizing the electrical characteristics of 55 nm BCD devices.