Design, modeling and comparative analysis of SRAM performance and functionality under the Subthreshold regime for various technologies

SRAM is widely recognized for its high storage density and fast access time, making it an essential component in VLSI chips. Its ease of use and minimal standby leakage contribute to its extensive application across various domains. In recent years, the increasing demand for secure and reliable user systems has further expanded its use beyond communication technologies to sectors such as transportation, industry, healthcare, and automotive systems. A CMOS-based SRAM cell is particularly advantageous due to its low power consumption and reduced read/write time. This article focuses on a 6T SRAM cell, known for its efficient use of power, space, and processing time during data operations. As a type of random-access memory, SRAM retains data for extended periods without requiring frequent circuit refreshes. This paper presents a performance analysis of a 6T SRAM cell implemented in 180nm, 90nm, and 45nm technology nodes, evaluating its write time (propagation delay) using the Cadence tool. The objective is to design a 6T SRAM structure that minimizes delay, as SRAM cells occupy a significant portion of a memory chip's area.