The Impact of Pid on The Degradation of LDMOS

Plasma-induced damage (PID) during semiconductor fabrication processes, such as inter-layer dielectric (ILD) and inter-metal dielectric (IMD) deposition and metal etching, poses significant challenges to device reliability. Generally, when gate oxide (GOX) thickness is above direct tunneling limit, PID is expected to decrease as the GOX thickness increases. Contrary to the conventional understanding, this work reveals that PID also contributes to the degradation of LDMOS devices with GOX thicknesses exceeding 10 nm, especially with field plate structure. It leads to the proposal of a novel hypothesis involving charge accumulation in or around the field plate. This work provides a novel perspective on the reliability of LDMOS and offers strategies to mitigate its adverse effects on LDMOS.