Dynamic Noise Sensitivity Based Critical Path Selection

Dynamic noise has become a critical concern in nanometer-scale digital integrated circuits (ICs), significantly affecting timing analysis and critical path identification. Traditional methods often overlook the impact of dynamic voltage fluctuations, leading to suboptimal optimization and potential timing violations. This paper proposes a dynamic noise sensitivity-based critical path selection methodology that incorporates logic gate noise sensitivity into path-level analysis. By accurately accounting for dynamic noise effects, our approach enhances the identification of critical paths most susceptible to timing issues. Experimental results on ISPD2012 benchmarks demonstrate that our method achieves higher accuracy than traditional techniques with minimal computational overhead, improving the reliability and performance of large-scale digital ICs.