Addressing Thermal Challenges in SOI with Silicon-on-Silicon Carbide Heterointegration

The buried oxide (BOX) of the Silicon-on-Insulator (SOI) inhibits heat dissipation from the Si film and leads to a significant self-heating effect (SHE). This article demonstrates a novel hetero-integration process and device architecture utilizing Silicon-on-Silicon Carbide (Si-on-SiC) technology to effectively address the thermal challenges in SOI. TCAD simulations of the SHE of this architecture are performed and compared with that of SOI. Under higher voltages at room temperature (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf>=V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</inf>=1.8V, 300 K), Si-on-SiC exhibits only 2.2% self-heating induced current degradation which is significantly improved compared to the 10.2% in SOI, while the maximum lattice temperature rises by 11.5 K which is also lower than the 57.9 K in SOI. Furthermore, standard high-k/metal gate CMOS process was developed for this novel substrate and both n- and p-type MOSFET devices were successfully fabricated, demonstrating that this SOI-like architecture is fully compatible with standard CMOS processes.