Timing Sequence Optimization Methods For Cross-Die Data Transmission

2.5D/3D SIC technologies are developing rapidly nowadays due to its many benefits. To optimize the data timing across dies, two methods are introduced including reserving setup/hold margins through using timing-margin optimization modules across die-interface and also including applying customized buffers with strong driving capabilities to reduce delay, so as to solve the timing problems of cross-die data transmission, increasing the test frequency and thus optimize the test cost of multi-die chips.