A Streamlined Electro-Thermal-Mechanical Simulation Method for Power Semiconductor Packaging Design

This paper demonstrates an efficient electro-thermal -mechanical simulation process for validating MOSFET packaging designs. Two PCB copper layouts and two packaging designs are discussed regarding to weak or risk points in current density and temperature distributions. Methods for validating solder joint electromigration and stress under power cycling are proposed. The study offers a streamlined simulation framework for packaging design of power semiconductor devices at operational currents.