Circuit Design and Sneak Path Current Analysis of 28NM 1T4R RRAM Memory IP

In recent years, with the fast advancement of emerging technologies, resistive random-access memory (RRAM) has emerged as one of the most promising memory technologies due to its compact size, low power consumption, fast read and write speed. Building upon the traditional one-transistor-one-resistor (1T1R) array, this paper proposes an innovative one-transistor-four-resistor (1T4R) array architecture that increases the integration density of the array. A 16×16 scale 1T4R memory IP has been designed on a commercial 28nm RRAM technology platform, and the impact of sneak path current on the array operation has been verified through simulation and testing. Additionally, a novel evaluation method has been proposed to analyze the relationship between sneak path current, array size, operating voltage, and the resistance value of the low-resistance state, where the feasibility and advantages of the 1T4R architecture in RRAM array design have been verified through simulations.