The Novel Strategy of Pattern Gate High Loading Controlling In ILD0 CMP Process

As the semiconductor device size reduced to 28nm or smaller, the high-k metal gate technology was gradually introduced into the chip manufacturing process to improve the response speed and reliability of devices. In the gate-last scheme, after metal gate chemical mechanical polishing (MG-CMP), the gate height in the short channel region is lower than that in the long channel region. The large pattern gate high loading leads to electrical anomalies eventually. In order to solve this problem, three methods based on inter-layer dielectric level zero chemical mechanical polishing (ILD0-CMP) were explored for controlling gate height loading in this paper, which are changing the polish stop layer, adjusting the selectivity of slurry and modifying the type of ILD0 oxide film. Under the controlling of ILD0-CMP, the transmission electron microscope result show gate height loading improved 57-97% and the gate height in weak device region increased 13%-47% post MG CMP process, the loop process window is enlarged.