A Novel 8T TFET-MOSFET Hybrid SRAM Cell for Ultra-Low Power and Computing In-Memory Applications

In this work, a novel 8T Tunnel FET (TFET)-MOSFET hybrid SRAM design with awareness of the impacts of large gate-drain capacitance in TFET is proposed and simulated. The proposed design utilizes MOSFET and TFET as upper and down transistor respectively in the read path, which can avoid the voltage coupling in conventional cascade TFET structure. Compared with conventional 6T CMOS SRAM, it achieves significant reduction in static and operation power, as well as improved static noise margin (SNM), leading to the lowest read power-delay-product (PDP). Moreover, its application for multiply-and-accumulate (MAC) operations in analog computing in-memory (CIM) is also demonstrated with high energy efficiency showing its great potential for energy-efficient AIoT applications.