A Self-Calibrated Digital-to-Time Converter with High-Resolution and Wide-Range Performance Using Multi-Level Tunable Delay Cells

Digital-to-time converter (DTC) is widely used in automatic test equipment (ATE) and electronic measurement systems. However, high-resolution and wide-range DTCs usually require a large chip area. This paper introduces a self-calibrated DTC based on multi-level tunable delay cells with high resolution, wide range, and good linearity. The design significantly reduces the chip area. The on-chip calibration circuit reduces the OCV effect, thus enabling on-chip calibration. In a 65nm process, the design achieves a linear adjustment range of 1ns using five 5-level coarse delay cells and twelve 6-level fine delay cells. The design has a resolution of 1ps, an INL range from -2.13 to 2.6LSB, and an area of 0.0022mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>.