Abnormal EPI Pattern Failure Mode Analysis with Virtual Farbication

In this paper, we use process models to explore different potential causes of abnormal epitaxy growth patterning, including variations in RCD (recess critical dimension) depth, EPI growth-blocking surface impurities and combinations of different growth rates in multiple directions. These abnormal epitaxial growth patterns can degrade transistor performance and cause device failures.We observed that a deeper RCD creates a shallower flat area on the patterned surface and can cause concave epitaxial patterns. After EPI cleaning, if there are surface impurities that block normal EPI growth, the resulting growth can produce a skewed pattern similar to simulating a defect placed on the <100> and <110> surface planes.Finally, we considered whether differences in growth rates at different crystal surfaces can arise due to the subsequent SC1 wet cleaning process and NH4OH evaporate left by weak air flow in the production tool. Our failure mode simulation of this effect was consistent with the conditions encountered on an actual production line. Using our failure mode simulation methodology, we developed a failure mode hypothesis using simulation and quickly resolved a production line problem based upon these simulation results.