Study of Breakdown Voltage Optimization in 1100V HVIC NLDMOS Devices
This study presents an in-depth investigation of the breakdown voltage characteristics of a 1100V High-Voltage Integrated Circuit (HVIC) NLDMOS device utilizing comprehensive two-dimensional TCAD simulations. Our findings indicate that the surface electric field can be significantly reduced by implementing P-type implant in the drift region. It is essential to optimize the energy and dose of the P-type implant in relation to the substrate resistivity, alongside the thickness and resistivity of the N-type epitaxial layer. The insights derived from this research pave the way for improved device design strategies aimed at enhancing breakdown voltage performance.
Authors
- Jun Hu (ORCID: https://orcid.org/0000-0002-4565-3000)
- Wenting Duan (ORCID: https://orcid.org/0000-0001-9665-4890)
- Shangze Wu (ORCID: https://orcid.org/0000-0002-3508-8415)
- Haiyang Ling
- Jian Ma
- Chunlei Wu (ORCID: https://orcid.org/0000-0002-6630-0757)
- Wensheng Qian (ORCID: https://orcid.org/0000-0001-9464-4242)
Institutions
- Fudan University (CN)
- Taiwan Semiconductor Manufacturing Company (China) (CN)
- Shanghai Fudan Microelectronics (China) (CN)
Publication Details
- Published
- 2025-03-24
- DOI
- https://doi.org/10.1109/cstic64481.2025.11017919
- Primary Topic
- Silicon Carbide Semiconductor Technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00