An Accuracy Scalable n-LDMOS Model for Drift Region

The scalable of breakdown voltage in LDMOS is usually achieved by optimizing the length of the drift region through layout structure without adding additional process steps. By adding the relationship between the device performances (IV and CV) and the drift region parameters in the sub-circuit model, a novel LDMOS model was introduced to achieve voltage scalability for both IV and CV prediction. This model has been validated with a 60V to 100V scalable LDMOS in 0.18μm process platform.