Design and Simulation of an Efficient Memristor based Full subtractor using Hybrid logic

Memristor-based digital circuits offer a promising solution to overcome CMOS limitations in scalability, speed, and power efficiency. This research explores the design of memristors, implementing digital circuits such as NAND gate, NOR gate, NOT gate, Multiplexer, and Full Subtractors. Simulations using MATLAB and LTspice evaluate performance, highlighting advantages like fast switching, non-volatility, and energy efficiency. These circuits were designed and simulated in MATLAB and LTspice using experimentally validated HP memristor model with precise current-voltage(V-I) characteristics. Comparative analysis underscores the potential of hybrid memristor -CMOS systems for next-generation memory and computational architectures. Circuit simulations assess the impact of memristor switching properties on energy consumption, reliability, and logic gate functionality. The memristors characteristics are integrated to enhance practical relevance. By addressing the current semiconductor challenges, this work establishes a foundation for more efficient and scalable digital circuits, advancing low power, high speed applications and paving the way for future innovations in computing and memory technologies.