Investigation of Performance Optimization in Bottom-Gate A-IGZO Thin-Film Transistors with Varying Thicknesses of PECVD-SiO₂ Gate Dielectric

In this work, bottom-gate a-IGZO TFTs with different thicknesses of PECVD-SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> gate dielectric and W/L ratios were fabricated. The device with a thicker gate dielectric exhibits the better performance with a V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</inf> of 72mV, a minimum SS of 155mV/dec, an I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON/OFF</inf> ratio of 3.72×10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup>, and an ultra-low leakage current of 1.23×10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-14</sup>A/μm since its superior interface quality. This unique effect may be attributed to the diffusion of residual hydrogen into the IGZO channel, which passivates interface defects and provides more free carriers in the thicker gate dielectric.