The Challenges and Solutions of Damascus Copper Process
The continuous scaling down in the logic device has presented numerous engineering and manufacturing challenges in Cu interconnection. High resistivity, poor reliability and insufficient filling capacity are encountered. The main failure mode are narrower top opening and discontinuous Cu seed at the sidewall. These weak points are trade off and the process has reached its limit. Excavating the maximum efficiency of the additives, optimizing plating current curve during gap fill and cooperation between pre & post process as well as fast root cause finding are very important. Three failure cases are analyzed in this paper, where it well discloses that smaller gap fill current during ECP is good for excavate the maximum efficiency of the additives, while it is not friend to Cu seed protection. A suitable current is request base on the failure model. Reliability problem is strongly correlate to cumulative thermal and airborne molecular contamination, so both equipment and Foup environment control is essential. Entry process of Cu plating is key step, in which a novel visible method is designed to simulate the liquid touch line evolution, thereby, to help solve pits defect after fully understand micro bubble trapping in the trench.
Authors
- Zhaoqin Zeng
- Yu Zhang (ORCID: https://orcid.org/0000-0002-8116-532X)
Institutions
- Shanghai Huali Microelectronics (China) (CN)
Publication Details
- Published
- 2025-03-24
- DOI
- https://doi.org/10.1109/cstic64481.2025.11017783
- Primary Topic
- Metallurgy and Cultural Artifacts
- Type
- article
- Field-Weighted Citation Impact
- 0.00