Research on EOS Damage of Chips Caused by Abnormal CPU Power-off Sequence

Recently, an issue that the product was not powered on has been claimed by our customers. As it has been identified as caused by a chip malfunction, a series of failure analysis was conducted on the failed chip. The test results of automatic test equipment (ATE) indicated that a short circuit abnormality existed in the power pin, VDDQ1_1P1, which was consistent with the I-V test results. No obvious abnormalities were found in the appearance inspection, scanning acoustic tomography (SAT), X-ray and other non-destructive testing. Subsequently, failure localization was carried out on the short circuited power pin and it was observed that the abnormal point was located in the DDR module inside the die, with obvious burn marks. After investigation, it was found that electrical over stress (EOS) damage was caused by abnormal power-off sequence. According to the circuit and power-off waveform analysis, adjusting the CPU power-off sequence to ensure that the VDD voltage of DrMOS is last powered off, should be adopted as the solution.