Vertical and Horizontal Profile Control in STI Etch

STI (Shallow trench isolation) Etch is a well-known method and widely used for active area isolation in FEOL [1] - [4]. The STI isolates each transistor from its adjacent transistor to prevent current leakage. Traditionally, this isolation is achieved through a LOCOS (localized oxidation of silicon) field oxide process. STI takes up less space while performing the same function as LOCOS, which in turn increases transistor density on the chip. CD and depth loading controlled by STI will become increasingly important to preserve the CD space, especially as the line and pitch size go down. This paper introduces shallow trench isolation method. Although there are various kinds of pattern and loading effect, the vertical profile is well controlled, and the elimination of depth loading effect are achieved, perfectly meeting the specification requirements.