The Structural Optimization of LDMOS with Low-Temperature-Oxide Field Plate

This work is dedicated to enhancing the electrical performance of high-voltage LDMOS devices based on 0.18μm BCD platform. It analyzes the key components of an LDMOS with the field plate structure that influence device performance, and systematically scales them to find the optimal combination. An appropriate TCAD simulation is employed to investigate the underlying mechanisms and to inform the strategies for enhancement. Ultimately, both the breakdown voltage and specific on-resistance of the device exceed the stipulated design criteria of a standard 35V LDMOS, which are 54V and 20.61 mΩ•mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>, respectively. Moreover, the figure of merit (FOM) demonstrates an improvement compared to the benchmark.