Etching Surface and Etching Dimension Control for IGZO TFT Fabrication in 3D Memory Device
We investigated etching processes to form transistor hole for indium-gallium-zinc oxide (IGZO) thin film transistors (TFT) in 3D memory device. A horn-shaped profile was achieved at top of the hole to avoid gate void exposure in the coming processes. Wet etching and gas etching methods were chosen to remove liner silicon oxide covering dummy poly in the hole. It was found that gas etching process resulted in smooth profile, leading to uniform IGZO thin film without metal aggregation.
Authors
- Hong‐Bo Sun (ORCID: https://orcid.org/0000-0003-2127-8610)
- Z. K. Hei (ORCID: https://orcid.org/0009-0002-4591-4968)
- Baodong Han
- Ganlin Song
- Guilei Wang (ORCID: https://orcid.org/0000-0002-1311-8863)
- Wenjun Chen (ORCID: https://orcid.org/0000-0002-0002-3013)
- Ming Zeng (ORCID: https://orcid.org/0000-0002-3708-1305)
- Liu Yang (ORCID: https://orcid.org/0000-0002-3034-6980)
- Xu Yang (ORCID: https://orcid.org/0000-0003-0292-5659)
- Jian Li (ORCID: https://orcid.org/0000-0003-3007-1443)
- Xiaodong Li (ORCID: https://orcid.org/0000-0002-6601-5788)
- Jiao Jin
- Chao Zhao (ORCID: https://orcid.org/0000-0002-4030-6384)
- Chunying Guan (ORCID: https://orcid.org/0000-0001-8692-7605)
- Zhonghua Jin
- Tuo Xin
Publication Details
- Published
- 2025-03-24
- DOI
- https://doi.org/10.1109/cstic64481.2025.11017774
- Primary Topic
- Thin-Film Transistor Technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00