Chiplet Dft Solutions for Cross-Die Testing Channels

Due to the quantity limit of IO in chiplet , the reusable IO resources for DFT (Design For Test) are relatively scarce in availability, which causes a significant bottleneck in testing process for DFT. In this paper, we propose a DLS (DFT Lane Switch) structure that allows flexible and efficient reuse of IO resources. Furthermore, we suggest reusing the UCIE (Universal Chiplet Interconnect Express) interconnect channels as test paths to increase the number of reusable channels across die. This solution increases the bandwidth of the test data, which help to reduce the time required for testing, then reduce the cost of testing. The channel switching scheme based on DLS is more suitable for chiplet, featured by a variety of packaging combinations.