Etching Process Optimization of Deep Silicon Trench Sidewall Damage with High Aspect Ratio

Deep trench etching process, as an important technology in the field of integrated circuit manufacturing, has been widely used in railway, new energy automobiles and smart grid in recent years. With the improvement of integration and device performance requirements, deep trench is developing towards higher aspect ratio and smaller CD, so that the deep trench etching process is facing severe challenges. As the aspect ratio increases, long-term exposure of the trench sidewall and hard mask to plasma results in sidewall damage and hard mask roughness which affect the device performance and production yield. In this paper, O<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>/SF<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</inf>/He is used as the plasma source based on the single step process (SSP) etching process, focusing on the sidewall damage and hard mask roughness in the deep trench etching process, the mechanism and improvement methods were studied by optimizing the parameters such as bias voltage, chamber pressure and gas flow. In addition, a new etching method was proposed, which effectively solved the problems of sidewall damage and hard mask roughness.