In-Device SEM-Based Overlay Metrology on VIA Layer of Logic Process

Device shrinkage requires continuous tightening of the overlay (OVL) control. Systematic deviation between optical after-develop inspection (ADI) and after-etch inspection (AEI) OVL, known as non-zero offset (NZO), is critically important when applied to the scanner process. In the 28 nm logic process, the VIA layer relies on accurate OVL control to ensure device yield. In this paper, we discuss in-device SEM-based OVL metrology of the VIA layer to demonstrate the NZO gap and enable a better corrective methodology to minimize NZO in the advanced process control (APC) loop. In addition, the SEM OVL is valuable for providing more detailed and comprehensive OVL distributions, enabling high-order correction of the scanner process.