Verification of PCIe over Electronic and Photonic I/Fs

High-speed computing (HPC) in data centers and for AI/ML computation relies largely on the high bandwidth and low latency of the interconnects between CPU, GPU, memory and storage. The high-speed serial computer expansion bus standard, peripheral component interconnect express (PCIe) 1.0 has been implemented since 2003 in CPUs and SoCs, including chip-to-chip through electronic interface (I/F) such as SerDes. Started at 2.5 GT/s, PCIe has been applied, from electronic I/F, over optic fiber or optics module. As released in 2022, PCIe 6.0 has become the latest standard to be studied over the photonic I/F. Meanwhile, the compute express link (CXL) was developed in 2019, we have initiated some study, 1) Using Alveo U50 FPGA platform for system verification of PCIe 4.0 supporting CCIX (now part of CXL) over electronic I/Fs; 2) Using Agilex 7 FPGA on high-speed Ethernet 400GbE data-rate through CMOS I/F SerDes; and 3) Based on I/F SerDes to fiber (E2O), and/or optic I/F to loopback to SerDes (O2E), the work was continued on CPO I/F. Current study aims at PCIe 5.0, at 32 GT/s or maximum 128 GB/s, over the Root Complex (host side) and the component side (endpoint side through on-board optic (OBO), to determine the system performance. The setup program for the electronic and photonic interconnect, system verification and results are presented.