Machine Learning to Model and Predict Layout Dependent Effects on 55nm Low Power Platform

Layout-dependent effects (LDEs) play a critical role in determining the performance of field-effect transistors (FETs), influencing key parameters such as threshold voltage (Vt), mobility, and saturation current (Idsat). These effects can significantly degrade the performance of mixed-signal integrated circuits fabricated on a 55nm low power platform. In this paper, we investigate two major LDEs: the length of diffusion (LOD) effect and the well proximity effect (WPE). A machine learning (ML) algorithm is developed to model and predict these effects, using testing data from devices under test (DUT). By employing a well-trained deep neural network (DNN) model, we analyze the FET characteristics (Vt and Idsat) and compare the results with those derived from both BSIM4 compact model SPICE simulations and Technology Computer-Aided Design (TCAD) simulations. Our results highlight the effectiveness of the ML-based approach as a powerful tool for modeling and predicting LDEs in the context of integrated circuit manufacturing.