A Novel Solution to Improve Reliability Characteristics of Advanced Node ETOX NOR-flash Memory

A novel solution to improve the top corner rounding of shallow trench isolation (STI) and time-dependent dielectric breakdown (TDDB) characteristics of peripheral circuit has been investigated in 4X-nm serial peripheral interface (SPI) NOR-flash memory cells with self-aligned STI architecture. The cell active area (CAA) last approach of integrated manufacturing process is implemented, where the CAA loop is formed after the completion of peripheral active area (PAA) loop, thereinto, the integrated PAA loop includes the process of peripheral STI trench etching, peripheral STI gap-filling, densification and planarization. Good peripheral STI top corner rounding and reliability results of peripheral MOSFET are obtained by process optimization of PAA loop. In this paper, the novel structure with CAA-last manufacturing process is provided to give insight into the improvement of reliability characteristics upon the shrunken cell geometry of advanced node NOR-flash technology featuring a self-aligned source ETOX architecture.