Zero Delay Cell Technology for Timing Optimization and Analysis in 3DIC Design

This paper introduces an innovative technology, Zero Delay Cell (ZDC), for timing analysis and optimization in 3DIC designs. The technology supplies an effective solution to solve the challenging problem of timing analysis optimization in 3DIC design. This paper defines a ZDC which achieves zero-delay transmission of signals, but no logical functionality. In the timing analysis, the zero-delay standard cell is used to build the timing circuit relationship between the top and bottom dies. When a signal is transmitted from one chip to another, its change can be immediate reflected at the corresponding zero-delay standard cell in the other chip, thereby completing the whole chip data transmission process without delay. Experimental results proved this technology can solve the timing optimization issues in 3DIC design. The method had been confirmed on real 3DIC design projects, proved its value in practical applications.