Power-Efficient Design of Full Adder Using XOR-XNOR Logic and Input-Controlled Leakage Restrainer Transistors in 14nm CMOS Technology

The reason for the rising importance of power efficiency in digital arithmetic circuits is the use of submicron CMOS technologies. This paper presents a new full adder design that uses XOR-XNOR logic with ICLRT technology and is fabricated using a 14nm CMOS process. It employs the ICLRT mechanism for dynamic control over leakage currents, thus minimizing power dissipation and enhancing performance metrics compared to other full adder designs.A detailed analysis of the proposed design shows significant reductions in leakage power and power-delay product, making it suitable for low-power and high- performance applications. The XOR- XNOR logic provides full-swing outputs, ensuring signal integrity while being scalable to wide word-length architectures.The full adder design has been simulated using advanced circuit design tools under process, voltage, and temperature variations to validate its robustness and reliability. The proposed approach demonstrates a comparative improvement in average power consumption, propagation delay, and PDP while remaining compatible with advanced requirements for VLSI integration. These results highlight the efficiency of this XOR-XNOR logic-based full adder design as a superior alternative for energy-efficient digital systems.