SPONGE: A Scalable Heterogeneous Chiplet Accelerator Architecture for Autonomous Driving

With advancements in packaging and die-to-die interconnect technologies, multi-chip modules (MCMs) offer a viable approach to building systems ranging from edge devices to data-center scales using fine-grained DNN chiplets. This approach significantly reduces both fabrication and design costs. However, there is currently no Chiplet accelerator specifically designed for autonomous driving scenarios. Thus, in this work, we propose a Scalable Heterogeneous Chiplet Accelerator architecture for Autonomous Driving, which consists of compute chiplets and a dual-functional IO chiplet. The compute chiplets include a global buffer, a computing engine, and a network communication engine. The dual-functional IO chiplet integrates interface IPs at its edge, with SRAM filling the central unused area enlarged by the edge IPs. These two types of chiplets can be freely combined to form various accelerator configurations. In addition, we propose a pipeline mapping strategy to efficiently utilize these compute and storage units. Overall, Sponge’s hardware and software optimizations reduce latency by $\mathbf{7 8. 2 \%}$ on average and reduce energy consumption by $53.6 \%$ compared to a baseline system using the state-of-the-art Tangram mapping strategy, optimized by us, across a wide range of DNNs.