A Comprehensive Investigation about Channel Size Effects on PBTI and SILC in Planar High-K MG NFETs

In this paper, a full-scale debate is under way on the effects of channel length and width on PBTI of High-K metal gate(High-K MG) NMOS device. The transistors used in this research are manufactured on Huali-28nm High-K MG CMOS platform. The experimental results shown that the PBTI induced Vt degradation declined when decrease the width of device. Gate leakage also exhibited strong correlation with channel size whether in strong or weak electric field. The underlying mechanisms are investigated and the results revealed it is attributed to the modulation of process related pre-exciting defects in the High-K bulk. Otherwise, PBTI stress applied at transistors with different gate length exhibiting two distinctly different degradation trends. This anomalous phenomenon is primarily stems from the effective work function(EWF) diversity between long and short transistors, this results in the actual voltage drop across gate oxide(Vox) existing discrepancies so too does the vertical electric field.