GIDL analysis of Novel 4F² VCT architecture using TCAD simulations

Vertical Channel Transistor (VCT) with 4F<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> cell architecture has garnered significant attentions owing to its relaxed channel dimensions, good gate control and potential for future 3D integration. Moreover, VCT with secondary epitaxial channel (eVCT) features controllable channel thicknesses and self-aligned gate dimensions, facilitating improved manufacturability. However, Gate-Induced Drain Leakage (GIDL) has become a critical factor in degrading the performance of eVCT. In this work, we investigate the GIDL effect in eVCT structure by TCAD simulations. We observe that as the channel thickness decreases, Band-to-Band Tunneling (BTBT) is significantly enhanced, resulting in a more pronounced leakage current. Furthermore, variations in channel length and doping concentration play significant role in the leakage characteristics of the transistors. Our findings underscore the critical importance of optimizing these parameters to effectively mitigate GIDL and improve the performance of eVCT, particularly in advanced memory applications.