Enhancing Reliability of Bipolar-CMOS-DMOS Technology Through Delicately STI Optimization

Bipolar-CMOS-DMOS technology encounters significant reliability challenges at advanced technique node, particularly under high gate and drain voltages. This study is dedicated to the optimization of the shallow trench isolation (STI) structure. By extending the thermal oxidation duration of the liner SiO2, achieving a marked improvement in the interface smoothness between the STI and silicon, thereby reducing electric field concentration. This approach effectively alleviates interface degradation and lowers parasitic resistance. Furthermore, the incorporation of SiN and SiON interlayers in STI helps suppress the hot carrier injection (HCI) at the drain, mitigating device degradation. Optimizing STI edge quality and structural design substantially improves the overall performance of BCD devices.