Study on Tungsten (W) Filling Void Improvement with Chamfered Gate Profiles

High-K/Metal Gate (HKMG) is one of the most remarkable innovations that enable scaling of Integrated Circuits (ICs). In the HKMG gate-last approach, dummy poly gate is removed and then Work Function Metal (WFM) layers are deposited, and finally the space is filled with Tungsten (W) using Chemical Vapor Deposition (CVD). Void-free W CVD has become challenging with High Aspect Ratio (HAR) brought by continuous device dimension scaling down. The existence of W voids results in increased risk of High-K exposure, which can potentially lead to Fin damage in the subsequent W etch back process and ultimately device failure. One way to eliminate W voids is to form a chamfered profile prior to W filling, which could be realized by pulling back SiN spacer at the dummy poly gate removal step or WFM during WFM BARC etch. In this paper, the two chamfered profile approaches — chamfered spacer (SP) approach and chamfered WFM approach — are studied systematically through virtual fabrication method. The impact of chamfered profile height and width on void volume and device yield are investigated. We found that shallow chamfered depth improves W filling without any voids forming, while deep chamfered profile leads to large voids instead. A void-free metal gate is beneficial for low RC delay, and with the same chamfered profile condition, SP approach has better RC performance compared the WFM approach. Through device simulation, the void-free metal gate was proven to have a stronger control on channel with a resulting boost in device performance.