Patterning Challenges and Perspectives Solutions in Advanced Dram Technology Nodes

Bit cost ($/Gb) is key indicator for memory company and measurable by die density. To drive the die density up ultimately, industry solution is memory array technology tended to real 3D structure, that resulted in certain critical layer’s pattern definition changed from horizontal to vertical direction, and patterning process is from traditional lithograph and etch to more module process like deposition, lithography, dry etch and wet etch etc., In order to overcome the new patterning challenge, module process co-optimization is must. In this paper, we evaluate the correlation between line CD uniformity and thin film roughness in 3D structure, and finally find a tunable knob to improve the CDU about 25%.