High-Performance and Power-Efficient FPGA Accelerator for Adder-Based Neural Networks

This paper presents a high-performance and energy-efficient FPGA-based accelerator for Adder Neural Networks (ANNs), designed to address the computational challenges in IoT applications. By eliminating traditional multiplication-intensive operations and adopting an adder-based computation model, the accelerator significantly reduces power consumption, memory bandwidth requirements, and processing delays. A novel near-memory computation (NMC) architecture is introduced to minimize off-chip memory access, enhancing both speed and energy efficiency. Extensive evaluations on AMD-Xilinx VC709 and KV260 FPGA platforms demonstrate superior performance, achieving 96.3% accuracy, lower DRAM usage (by 45.5%), and 50% lower power consumption than CNN-based counterparts. These results position the proposed ANN accelerator as an optimal solution for real-time, scalable, and power-efficient AI-driven IoT applications.