A Reconfigurable Switched-Capacitor RF Receiver for Low-Power Applications

This paper presents a novel RF receiver architecture that combines specific harmonic rejection, switched-capacitor filtering, and current-reuse techniques to achieve high performance with low power consumption. The proposed receiver utilizes a reconfigurable switched-capacitor filter to selectively reject undesired harmonics generated by the local oscillator, thereby improving signal integrity and reducing interference. The filter’s programmability allows for dynamic adaptation to varying RF environments, making it suitable for a wide range of applications. Current-reuse techniques are employed to enhance the receiver’s noise figure without significantly increasing power consumption. The proposed architecture is implemented in a standard CMOS process, and simulation results demonstrate its effectiveness in achieving high linearity, low noise, and good harmonic rejection while maintaining low power consumption. The combination of reconfigurability, low power, and robustness makes this receiver an attractive solution for next-generation wireless communication systems.