Research on the Application of DED Process in Embedded Semi-Floating Gate

The embedded semi-floating gate (SFG) structure is characterized by its gate with charge storage capability. However, during the embedded processes for array integration, this structure can lead to challenges such as high aspect ratio of poly trench etching and the formation of poly voids during poly filling. Additionally, it will produce step height which cause surface damage to logic circuits during poly chemical mechanical polishing (CMP). To address these issues, this paper proposed the use of a DED (deposition-etch-deposition) method. By reducing the trench aspect ratio and optimizing poly deposition, combined with a skip poly CMP process integration, we have achieved void-free poly deposition while minimizing poly pattern loading, thereby effectively protecting the logic circuits.