A Dynamic Congestion-Aware Analytic Initial Routing Flow for VLSI Designs

Initial routing is one critical step of global routing at the early stage. A recent work forms initial routing as differentiable models and achieves better routing quality by deploying it on GPUs for efficient parallel optimization. However, it still lacks enough considerations on congestion without fine-grained global layout conditions. In this work, we propose a dynamic congestion-aware analytic initial routing flow, where methods are proposed to iteratively prune nets, generate congestion-aware tree candidates, and perform tree updating. The congestion estimation becomes more precise through this procedure to provide a better solution. According to the experiments on ISPD’24 contest and ICCAD’19 contest benchmarks, the proposed flow can achieve 16.8% and 46.5% less overflow on average after global routing, compared with two state-of-the-art global routers.