Solution to Sidewall Roughness of High Aspect Ratio TSV Etch in Advanced Packaging

Through silicon via (TSV) etch is a crucial process in chip manufacturing, especially in advanced packaging. TSVs are used to connect vertically stacked chips, resulting in short interconnections between chips and reduced device latency. With the increasing aspect ratio (AR) of TSV, the balance between passivation and etch is more difficult to control during the TSV etch, resulting in more sidewall roughness issues. For high aspect ratio (HAR, AR>10) TSVs, the most challenging sidewall roughness issues include Si damage, striations and the trade-off between the two. These sidewall roughness issues degrade post metal filling in TSVs and the final electrical properties of the device. In this paper, the TSV sidewall roughness mitigation approaches are studied with Lam Research’s Syndion<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> Etcher. The trade-off between Si damage and striation is broken by effective passivation management along the formation of TSV. Si damage formed at the top of the TSVs is mitigated by shorter precoat time, and lower bias voltage in RAP passivation phase. And the striation formed in the middle of the TSVs is mitigated by lower bias voltage and higher pressure in RAP passivation phase. Top damage and middle striation free HAR TSV etching is achieved in Syndion. This provides TSV benchmark solution for advanced packaging.