Stuck-At and At-Speed Interconnect Tests for 3D-IC

With the increasing complexity of integrated circuits, it is much more difficult to reduce the chip size, the 3D-IC technique is a promising approach to solve this problem by stacking dies fabricated by different foundries with the most efficient technology node. But only the concerns about heat dissipation, yield, and test cost are solved then the 3D-IC can be large-scale commercial used<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1]</sup>. When the chips are stacked together, the data switch between different dies mainly relies on the interconnect between the stacked dies such as micro-bumps, a cluster of TSVs and so on. So the interconnect test plays a important role in the stacked chip defects screening by adding effective design-for-test (DFT) features to fully test the interconnects. In this paper, a die wrapper register (DWR) structure based on IEEE1838 standard [2] is introduced which can be used to test not only the stuck-at fault, but also the transition fault of the interconnects. As for the at-speed test, the synchronous OCC(on-chip-clock) logic is also used to test the register-to-register at-speed inter-die path. Depending on the specific defects that need to be detected, the SCAN/JTAG switch logic used in the design can be configured. So the DWRs can also function as boundary scan cells during Know-Good-Die (KGD) test stage by connecting the DWRs to the JTAG network. And the use of scan logic for interconnect test can support fault diagnose which plays an important role in improving yield of 3D-IC.