A High Efficiency and Reconfigurable Neuromorphic Engine with Parallel – Pipeline Pooling Scheme

This paper developed a very high-energy-efficiency neuromorphic chip is proposed and demonstrated with 55nm CMOS technology which is free-expandible to the suitable scales to meet the requirement of various AI applications. A novel compact even-driven near-memory MAC module is proposed based on binary spiking neural networks (BSNNs) to minimize both memory volume and memory access. Additionally, a parallel-pipeline pooling scheme is adopted using a multi-threaded post-convolutional max-pooling computation, to further reduce the data access for intermediate results during convolution processing. The prototype chip with four MAC modules was designed and fabricated under 55nm-CMOS technology for image recognition. The chip results verified a high-energy efficiency of 21.08TOPS/W @1.2V/ 100MHz with a handwritten-digit recognition accuracy of 96.92%.